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REBUS SystemThe M.I.T. Enterprise Forum -- a non-profit, volunteer organization for the support and promotion of high-tech entrepreneurship in the greater Washington D.C. and Baltimore area -- held its first Tech Transfer Lab Event in January this year. The purpose of the event was to identify scientific achievements from the area that are particularly suited to being put into practice. One of the GW CS Department faculty, Prof. Simon Berkovich, was among only five whose work was invited for presentation at the event. The other invited presenters were from George Mason University and University of Maryland at College park. A panel of well-known entrepreneurs then discussed what it would take to bring the presented ideas to the market.Prof. Berkovich's presentation, on A Combinatorial Architecture for Instruction-Level Parallelism, has received considerable commercial attention since the presentation. In particular, SNAPP (Shared Network Acceleration Parallel Processing) Technologies is interested in licensing and commercializing the idea, which was patented by Prof. Berkovich and his collaborator, E. Berkovich, in 1997. The technology of the invention relates to a novel principle for microprocessor design called REBUS. As the performance of microprocessors reaches their principal physical limits, further improvements in computational power require innovative computer solutions. The REBUS processor provides such a solution. Additionally, it also dissipates less heat and spreads it over a bigger area. The idea is based on a pairwise balanced combinatorial arrangement of processing and memory elements, to allow concurrent processing of data independent instructions. Because the partitioning is done at compile-time, this design extracts substantial Instruction-Level Parallelism from executable code without the overhead of run-time methods. The generation of executable code requires minor adjustments to a standard compiler, and the hardware is built of regular modular components, making the design straightforward to implement. Prof. Berkovich's doctoral student, Alexander Kuznetsov, took this idea further by suggesting a method for adding router functions to the REBUS architecture. The patent application for this idea is in preparation. For more information, see: 1. "Method and Apparatus for Concurrent Execution of Serial Computing Instructions Using Combinatorial Architecture for Program Partitioning", US Patent No 5,619,680, issued April 8, 1997. 2. E. Berkovich and S. Berkovich. "A Combinatorial Architecture for Instruction-Level Parallelism". Microprocessors and Microsystems, Vol. 22, pp. 23-31, 1998. |
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